We use cookies to deliver our services. By visiting our website, you agree to the use of cookies as described in our  Privacy Policy.
Click here to hide this one-time notice.

Daijob.com is Japan's definitive job site for multilingual professionals.

Job Search

keyvisual
Updated 2024-04-09
Activated 2024-04-03

Logic Design and Verification Engineer

  • Recruiter
  • Executive Level
  • Women Welcome
  • Reduced Work-Hours
  • Five Days Workweek
  • English Language Skills
  • Foreign Affiliated Company
  • Publicly Listed Company
  • Urgent Hiring
  • Global Company
  • Experience Welcome
This posting is managed by: Fidel Consulting KK
Company Name Company is not publicly visible
Job Type
Fidel Consulting KK
IT (PC, Web, Unix) - Web Application SE
IT (PC, Web, Unix) - Database SE
IT (Mainframe) - Application SE
Location Asia Japan Tokyo

Job Description Logic design and verification of microcomputers for use in vehicles
Logic design for LSIs.
Verilog-HDL must be literate and capable of running simulations
There is no actual machine evaluation, etc., and it is a full day desk software job with some hardware involved. Even if you don't have enough experience, if you are a young person and work hard, we will do OJT within the team.
Analyze complex and critical software interfaces and suggest improvements
Planning, scheduling, monitoring, and reporting on software-related activities for various projects
Responsible for the software development, good communication skills to work with cross-functional team.
Apply principles of SDLC and methodologies like Lean/Agile
Self-driven and strong inter-personal skills
Company Info Over 300 customers, including 40% of the top 100 global innovators, to deliver intelligent engineering and technology solutions for creating a digital, autonomous, and sustainable future. As a company, is committed to designing a culturally inclusive, socially responsible, and environmentally sustainable Tomorrow Together with our stakeholders.
Job
Requirements
Good knowledge on VerilogUnix
Logic validation tools (Synopsys/Cadence)
Logic design for LSIs. Verilog-HDL must be literate and capable of running simulations.
Have communication skills because it is a team job
English Level Business Conversation Level (TOEIC 735-860)
Japanese Level Business Level(JLPT Level 2 or N2)
Salary JPY - Japanese Yen JPY 3000K - JPY 7000K   
Back

Logic Design and Verification Engineer

Apply
Like