Power Management Hardware Engineer @ Vietnam | Global Career Agent Inc.の求人詳細


キービジュアル キービジュアル
更新日 2019-08-09
掲載開始日 2019-08-09

Power Management Hardware Engineer @ Vietnam

  • ★★ スタッフレベル
  • 中高年歓迎
Global Career Agent Inc.
企業名 会社名非公開
職種 電機(電気/電子/半導体) - セールスエンジニア/サービスエンジニア
電機(電気/電子/半導体) - 基礎研究開発
機械(自動車/プラント/精密機器) - 基礎研究開発
業種 半導体・電気・電子部品メーカー
勤務地 アジア ベトナム

仕事内容 The scope includes design and optimization of Chipset PCB Floorplan, Schematic, Layout, Device thermal solution and eBOM selection for specific projects.
The engineer is required to perform the required board level simulations (based on Power Integrity and Signal Integrity tools) to review and sign off on hardware designs developed by teams.
The engineer will be responsible for characterizing and publishing performance and cost optimized reference BOM lists (power inductors, capacitors, third party components, etc.) based on component characterization and BOM reduction and optimization tests in lab.
Qualcomm PMIC hardware design typically consists of modules such as switch-mode power supplies and linear voltage regulators for a variety of cores and peripherals, battery chargers, low noise clocks, ADCs, user interfaces such as display, camera flash and haptics, Power-on and Reset hardware.

Other Keywords: パワー・マネージメント、回路設計、DC-DCコンバーター、省電力機能、保護回路
The world's largest fabless semiconductor producer and the largest provider of wireless chipset and software technology. Top class innovator with yearly R&D spend over USD$3B. Market Capatization at USD$120B
応募条件 The engineer will design schematic, PCB layout and BOM selection.
Experience in Mentor/Cadence design tools is desirable.
Understanding and ability to apply electrical engineering concepts and circuit solving skills.
Able to work with common lab test equipment (oscilloscope, spectrum analyzer, logic analyzer, network and impedance analyzer, etc.).
Experience in Power Management (SMPS, LDO, battery chargers, Clocks, ADC) PCB design and component selection including CAD interface.
Experience in high layer count multilayer boards (6/8/10 layers) preferred.
Good understanding of common Signal and Power Integrity issues on test hardware and ability to identify and provide alternate solutions using Signal and Power Integrity simulators (e.g. PowerSI, SIWave, Ansys) is also a plus.

英語能力 ビジネス会話 (TOEIC 735-860)
日本語能力 流暢(日本語能力試験1級又はN1)
年収 経験と能力に基づく   
契約期間 Permanent
最寄り駅 Tokyo

Power Management Hardware Engineer @ Vietnam