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キービジュアル キービジュアル
更新日 2018-10-10
掲載開始日 2018-10-09

RTL Engineer

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この求人の
取扱い会社
人材紹介
T.A.O Group K.K.( Stepfirst )
企業名 会社名非公開
職種
T.A.O Group K.K.( Stepfirst )
電機(電気/電子/半導体) - 設計/CAD設計/CADオペレータ
電機(電気/電子/半導体) - その他
業種 半導体・電気・電子部品メーカー
勤務地 アジア 日本 神奈川県

仕事内容 RTL Designer
Atsugi

Job Description

Digital Design Leader Required Qualifications:
Minimum 10 years of solid experience in SoC design, with experience managing large teams Good knowledge of Digital Design and RTL development
Hands-on experience with SoC Design, Verilog RTL coding Create/ work on designs using Power domain & Low Power Design techniques.
Hands on in Clock Domain Crossing (CDC) checks, Linting, equivalence checks and Synthesis
Understanding of Bus protocols (AHB/AXI etc), interconnects, peripherals, DDR, clock & resets
Understanding of Memory controller designs and Microprocessors is desirable

Be an individual contributor in the design
Tasks Architecting ASIC designs, micro-architecting, RTL coding of design, debug etc.
Understanding of Chip IO design and packaging is desirable
Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification
Manage IP dependencies, planning and tracking of all front end design related tasks
Driving the project milestones across the design, verification and physical implementations Experience in managing a team of talented engineers
Needs to make effective and timely decisions, even with incomplete information.
Provides direction, mentoring, and leadership to small to medium sized groups.
Should possess effective communication and leadership skills
Good people management, team work skills and strong positive attitude are essential
Good Writing and Speaking Skills in English and Japanese (For Japanese Leader)

Optional Skills:
Understanding of System Verilog based verification
Experience with FPGA realizations of higher complexity designs
Experience of synthesis and back-end flows and tools
Experience in Low power design

Brief Description of the Project/Assignment:
The project involves development and verification of digital designs for ASICs and FPGAs using Verilog or System Verilog to meet functional and performance requirements.

Roles and Responsibilities:
Capture technical requirements from the Japanese customer
Technically lead a small team of RTL designers both at onsite and offshore to meet project objectives.
Communicate directly with the customer on any technical issues and offer solutions if required.
Assure the quality of the deliverables from the team before delivering to customer.
Fulfill the customer expectations. Min.
応募条件 RTL Engineer
Japanese and English
Qualification B.E/B.Tech in Electronics
Job Type (Permanent/ Contract) Permanent
Job Location Kanagawa, Japan
英語能力 ビジネス会話 (TOEIC 735-860)
日本語能力 流暢(日本語能力試験1級又はN1)
年収 経験と能力に基づく   
給与に関する説明 Social Insurance
Commuting/Transportation Allowance
休日 Five-Day Workweek
Paid Holidays
契約期間 Full-time
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