|This posting is managed by:||
RecruiterRGF Talent Solutions Japan K.K. (RGF Professional Recruitment Japan)
|Company Name||TSMC Design Technology Japan Inc.|
Electronics (Appliance/Semiconductor) - Design/CAD Design/CAD Operator
Electronics (Appliance/Semiconductor) - Project/Production Manager
Electronics (Appliance/Semiconductor) - Valuation/Testing
|Industry||Electronics, Components, and Semiconductor Manufacturing|
Automatic placement and routing for advanced technology
Implementation, Netlist (RTL)-GDS design flow, depending on your experience.
Depending on your experience and skills, we can prepare a position as a technical manager.
-Chip/block level floor plan creation
-Clock tree synthesis
-Place and route
-RC extraction, STA, timing design
-IR/EM analysis, correction
-DRC / LVS / ERC analysis, correction
-Automatic wiring flow development
<Global leading company that has been a pioneer of specialized foundry business model since its establishment in 1987>
For industry customers and partners around the world, with industry-leading process technology,
Providing an ecosystem that enables product design, and bringing innovation to the global semiconductor industry.
First successful in mass production of 7nm process and commercialization of EUV lithography technology.
<Opportunities we can provide to you>
In collaboration with the world-class design team, in the world-class design service ecosystem,
By participating in the world's most advanced semiconductor technology development including 5nm process, 3nm process, and further advanced nodes,
You can hone your skills and leadership skills.
We have the opportunity to support major customers worldwide, and we offer cutting-edge products that transform our daily lives.
You can contribute to the world.
Realize semiconductor innovation by engaging in development and optimization in all aspects of the Pre-Silicon design flow.
-Support for APR based on customer's request
-Design-process co-optimization, development of internal test chip
-Development of SRAM macros and compilers for Foundation IP development
-Design flow development that enables APR of processes
-Synthesis, floor plan, APR, timing/power signoff & physical verification
-Over 3 years of work experience in layout design or design flow construction
-Experience using script language (shell, Python, TCL) or C/C++
-Experience using automatic wiring tools (Cadence/Innovus, Synopsys/IC Compiler II, etc.)
-Design experience in process nodes of 28nm and below (FinFET layout experience from 16nm and beyond is welcome)
-English ability for technical discussion
-Excellent customer orientation
-Willingness to learn, willingness to solve problems
-Skilled communication skills and team play
-Person with a strong sense of responsibility
|English Level||Business Conversation Level (TOEIC 735-860)|
|Japanese Level||Business Level(JLPT Level 2 or N2)|
|Salary||JPY - Japanese Yen JPY 8000K - JPY 15000K|
RGF Talent Solutions Japan K.K. (RGF Professional Recruitment Japan)